Plug for Verilator
Friday, October 24th, 2008 by laneI am a dedicated user and contributor to open source software. I have long wished that semiconductor companies would ban together and shift their resources from paying closed-source EDA companies and instead hire software engineers to develop open source CAD tools. I think the result would be a much better CAD environment.
The advent of the Fedora Electronics Lab (FEL) raised the awareness to me of a few open source projects that have become quite mature and good–including Icarus Verilog and GTK Wave. I am now using Icarus verilog as my simulation tool of choice for quick and dirty verification of small designs or library modules. GTK Wave is also quite good as a near replica of simvision. I no longer have a need verilog-XL or simvision. I found the performance Icarus verilog lacking, however, for large scale design (in the same way verilog-XL).
When reading through something on Icarus verilog in a forum or something,someone mentioned the speed of Verilator. I had never heard of Verilator, but a quick Google search led me there. It did not take me long to realize the design principles behind Verilator are exactly what I have been looking for in a digital simulator. Here is why:
- It slices the feature support at the perfect place. Verilator does not support unsynthesizable code. I find this to be pure genius. I can model my unsynthesizable code in a language that is much better suited for that (like C/C++, python, etc). This is such a natural thing to do for a simulator whose goal is performance.
- It is open source.
- It is fast and able to handle large designs.
The only feature that it lacks that I do find quite problematic is “tri-states” or “inouts”. Hopefully this can get alleviated soon. It has quirks that I embrace completely. For example, it does not support the unknown state “X”. On startup, everything is initialized high, low, or randomly. This is an example of a tradeoff that is perfectly reasonable to maximize performance. When you want to verify that your chip is starting up correctly and that everything pulls out of reset, use a more feature complete simulator like Icarus verilog. When you want to run a simulation that needs every last bit of performance, forgo “X” support and use Verilator.
I now have a large design project that I have brought up in verilator. It is quite a pleasure to work with. I have created a python extension module written as a C++ wrapper around the simulation that lets me control and evaluate everything using a nice higher level language. This is the most fun I have had with simulations in a long time. I had done a similar thing for NC-Verilog using the PLI interface, but it was not nearly as pleasant as Verilator–largley because Verilator is open source and I could modify the build process to produce a shared library. The beauty of making the python extension module is that I can implement all the time consuming operations in C++ for maximum performance, while doing the higher level tasks in python. I have integrated numpy into the extension module as well, so I can work with and analyze arrays very efficiently and then I use matplotlib to plot the simulation results.
I will post a short a little “getting started” example soon on how to build a python extension module around a Verilator simulation. For now I just wanted to make a plug for Verilator. I wish I had discovered it years ago. I will no longer be using the likes of VCS or NC-verilog again.